Multi-port semiconductor memory device having variable access paths and method therefor

ABSTRACT

A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

CROSS-REFERENCE TO RELATED APPLICATION

The above-referenced application is a Continuation of U.S. Ser. No.11/466,389, filed on Aug. 22, 2006, now pending, which claims priorityunder 35 U.S.C. § 119 from Korean Patent Application No. 2005-127534,filed Dec. 22, 2005, the disclosure of which is hereby incorporatedherein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Technical Field

The invention relates to multi-port semiconductor memory devices havingvariable access paths and, more particularly, to a semiconductor memorydevice and a method for performing a normal operation or a testoperation by variably controlling access paths between a plurality ofinput/output ports and a plurality of memory areas.

2. Discussion of Related Art

In general, semiconductor memory devices such as random access memories(RAMs) include one port having a number of input/output pin sets inorder to communicate with an external processor.

FIG. 1 illustrates a conventional semiconductor memory device havingfour memory banks and a single input/output port. The conventionalsemiconductor memory device includes a memory array 10 having fourmemory banks 10 a, 10 b, 10 c and 10 d, and a port control unit 20 forcontrolling a single input/output port. The port control unit 20includes control circuits for controlling a command signal, an addresssignal, a data signal, and other signals input or output through theinput/output port. All of the memory banks 10 a, 10 b, 10 c and 10 d areaccessed through the port control unit 20. The arrows indicate theaccess paths.

The conventional semiconductor memory device having a singleinput/output port has problems with access speed and access efficiency.For example, to perform a first operation of storing first data in the Abank 10 a and a second operation of reading second data from the B bank,which is distinct from the first operation, the semiconductor memorydevice must perform the operations sequentially, the first operation andthen the second operation or vice versa. This is not suitable for highspeed and high efficiency.

For higher speed and greater efficiency, a multi-port semiconductormemory device that performs communication through a plurality ofprocessors and has memory cells that can be accessed through a pluralityof input/output ports has been developed. An example of such aconventional multi-port semiconductor memory device is disclosed in U.S.Pat. No. 5,815,456, Sep. 29, 1998.

Generally, the conventional multi-port semiconductor memory device mayhave several structures to enable accessing of memory cells. Threerepresentative structures include: (1) a structure allowing all memorycells to be accessed through any of a plurality of input/output ports;(2) a structure allowing each memory cell to be accessed only throughfixed input/output ports; and (3) a structure allowing specific memorycells to be accessed only through fixed input/output ports and anyremaining memory cells to be accessed through any ports.

In these structures, because access paths between the input/output portsand the memory cells are prescribed in hardware, a change among thestructures is impossible. That is, a user is not allowed to change, forexample, (1) the structure allowing all memory cells to be accessedthrough any of a plurality of input/output ports, into (2) the structureallowing each memory cell to be accessed only through fixed input/outputports. This inflexibility degrades operational efficiency of themulti-port semiconductor memory device. In addition, since a test shouldbe separately performed through each input/output port, thisinflexibility also degrades test efficiency.

SUMMARY OF THE INVENTION

One aspect of the invention is a semiconductor memory device having aplurality of input/output ports; a memory array divided into a pluralityof memory areas; and a select control unit to establish variable accesspaths between the memory areas and the input/output ports so that eachmemory area is accessed through at least one of the input/output ports.

Another aspect of the invention is, in a semiconductor memory devicecomprising a plurality of input/output ports and a memory array dividedinto a plurality of memory areas, a method for variably accessing thememory areas includes allocating the memory areas for access through atleast one of the input/output ports and establishing data and addresspaths between the memory areas and corresponding input/output portsaccording to the memory area allocation. The method further includesre-applying the external command signals to re-allocate the memory areasfor access through different input/output ports and establishing newdata and address paths between the memory areas and the differentinput/output ports according to the memory area re-allocation.

Yet another aspect of the invention provides a method for testing amulti-port semiconductor memory device comprising a plurality ofinput/output ports and a memory array divided into a plurality of memoryareas, the method including: allocating the memory areas to eachinput/output port, so that each memory area is accessed through at leastone of the input/output ports; and testing the allocated memory areasthrough each corresponding input/output port. The method for testing mayfurther include re-allocating the memory areas, so that each memory areais access through different input/output ports; and testing there-allocated memory areas through the corresponding differentinput/output ports.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of embodiments of theinvention will become readily apparent by reference to the followingdetailed description when considered in conjunction with theaccompanying drawings in which:

FIG. 1 illustrates access paths of a conventional semiconductor memorydevice having four memory banks and a single input/output port;

FIG. 2 is a schematic block diagram illustrating a multi-portsemiconductor memory device according to an embodiment of the invention;

FIG. 3 is a block diagram illustrating a select control unit 400 a andfirst and second port control units 200 a and 300 a for an A bank inFIG. 2;

FIG. 4 is a circuit diagram of a first command multiplexer of FIG. 3;

FIG. 5 is a circuit diagram illustrating a row address multiplexer ofFIG. 3;

FIG. 6 is a circuit diagram illustrating a first data sense amplifier ofFIG. 3;

FIG. 7 is a circuit diagram illustrating a first data driver of FIG. 3;

FIG. 8 is a circuit diagram illustrating a first data multiplexer ofFIG. 3; and

FIGS. 9 to 15 illustrate an example of an access path control operationin a semiconductor memory device according to an embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

As will be apparent to those skilled in the art from the followingdisclosure, the invention as described herein may be embodied in manydifferent forms and should not be construed as being limited to thespecific embodiments set forth herein. Rather, these embodiments areprovided so that this disclosure will fully convey the principles of theinvention to those skilled in the art. In the drawings, the thicknessesof layers and regions are exaggerated for clarity.

For convenience of understanding, a multi-port semiconductor memorydevice having two input/output ports will be described. However, it willbe appreciated by those skilled in the art that the invention may beapplied to a multi-port semiconductor memory device having two or moreinput/output ports.

FIG. 2 is a schematic block diagram illustrating a multi-portsemiconductor memory device according to an embodiment of the invention.The multi-port semiconductor memory device includes a memory array 100,a first port control unit 200 for controlling signals input or outputthrough a first input/output port, a second port control unit 300 forcontrolling signals input or output through a second input/output portdifferent from the first input/output port, and a select control unit400.

The memory array 100 is divided into a plurality of different memoryareas. For example, the memory array may be divided into four memorybanks 100 a, 100 b, 100 c and 100 d, as in a typical semiconductormemory device.

It is to be understood that the first port control unit 200 and thesecond port control unit 300 include the first input/output port and thesecond input/output port, respectively. The first port control unit 200includes control circuits for controlling a command signal, an addresssignal, a data signal, and other signals input or output through thefirst input/output port. Similarly, the second port control unit 300includes control circuits for controlling a command signal, an addresssignal, a data signal, and other signals input or output through thesecond input/output port.

The select control unit 400 performs a memory allocation operation thatcontrols a data path and an address path between the input/output portsand the memory areas constituting the memory array 100. That is, theselect control unit 400 preferably controls access paths between thememory areas and the input/output ports so that each memory area may bevariably accessed through at least one of the input/output ports. Forexample, the select control unit 400 controls the access path tovariably allocate each of the four memory banks 100 a, 100 b, 100 c and100 d as one of a first input/output port dedicated access area, asecond input/output port dedicated access area, and a shared accessarea.

The select control unit 400 may perform a memory allocation operation inresponse to a mode register set (MRS) signal for a normal operation andin response to an MRS signal for a test operation. The select controlunit 400 may also operate in response to a command signal generated byany external command signals normally applied for operation of thesemiconductor memory device or a combination of the external commandsignals, which are not the MRS signal. The external command signals maybe separate, independent signals that each correspond to the memoryareas.

FIG. 3 is a block diagram illustrating an example of a select controlunit 400 a and first and second port control units 200 a and 300 a forallocating one memory bank (e.g., A bank 100 a) to the first or secondinput/output port in FIG. 2. A select control unit 400 a and first andsecond port control units 200 a and 300 a shown in FIG. 3 are for onlyone memory bank (e.g., A bank 100 a). Accordingly, as will beappreciated by those skilled in the art, if the semiconductor memorydevice has a plurality of memory banks, a select control unit and portcontrol units for each memory bank may be similarly configured as theselect control unit 400 a and the first and second port control units200 a and 300 a.

The A bank 100 a in the memory array 100 of FIGS. 2 and 3 may refer toone of a plurality of memory banks in a typical semiconductor memorydevice. The A bank 100 a may also refer to an internal sub blockconstituting a memory bank, which is a smaller unit than a typicalmemory bank. The A bank 100 a may also refer to a combination of two ormore memory banks.

Each memory cell in the A bank 100 is selected by one of word lines WLand one of bit lines BL. A row decoder 110 for selecting the word lineWL in the A bank 100 a and a column decoder 120 for selecting the bitline BL in the A bank 100 a are provided around the A bank 100 a.

The first port control unit 200 a includes a first data sense amplifier210 and a first data driver 220 for controlling data input to or outputfrom the A bank through the first input/output port. The first portcontrol unit 200 a may additionally include a data buffer circuit or alatch circuit for controlling data input and output. The first portcontrol unit 200 a may further include control circuits (e.g., commandbuffer circuit, command latch circuit, address latch circuit, andaddress buffer circuit) for controlling command signals (e.g., bankselect signal CMD_A1, RAS signal, CAS signal, write command signal, andread command signal) and the address signal ADD_1 input through thefirst input/output port. Here, the first data sense amplifier 210 is forread operation of data Dout_1 stored in the A bank 100 a and outputtingdata Dout_1, and the first data driver 220 is for write operation ofexternal input data Din_1 and storing data Din_1 in the A bank 100 a.

The second port control unit 300 a includes a second data senseamplifier 310 and a second data driver 320 for controlling data input toor output from the A bank through the second input/output port. Thesecond port control unit 300 a may additionally include a data buffercircuit or a latch circuit for controlling data input and output. Thesecond port control unit 300 a may further include control circuits(e.g., command buffer circuit, command latch circuit, address latchcircuit, and address buffer circuit) for controlling command signals(e.g., bank select signal CMD_A2, RAS signal, CAS signal, write commandsignal, and read command signal) and the address signal ADD_2 inputthrough the second input/output port. Here, the second data senseamplifier 310 is for read operation of data Dout_2 stored in the A bank100 a and outputting data Dout_2, and the second data driver 320 is forwrite operation of external input data Din_2 and storing data Din_2 inthe A bank 100 a.

The select control unit 400 a includes a command multiplexer portionincluding a first command multiplexer 410 and a second commandmultiplexer 460, a data multiplexer portion including a first datamultiplexer 420 and a second data multiplexer 430, and an addressmultiplexer portion including a row address multiplexer 440 and a columnaddress multiplexer 450.

The command multiplexer portion 410 and 460 generates select controlsignals ICMD_1 and ICMD_2 for allocating the A bank 100 a as one of afirst input/output port dedicated access area, a second input/outputport dedicated access area, and a shared access area. The first commandmultiplexer 410 generates a first select control signal ICMD_1 for thefirst input/output port in response to an A bank select signal CMD_A1that is a command signal for selecting the A bank 100 a, and access pathcontrol command signals Fix_1 and Shared. The first select controlsignal ICMD_1 controls the access path to set the A bank 100 a as one ofthe first input/output port dedicated access area and the shared accessarea.

The second command multiplexer 460 generates a second select controlsignal ICMD_2 for the second input/output port in response to an A bankselect signal CMD_A2 that is a command signal for selecting the A bank100 a, and access path control command signals Fix_2 and Shared. Thesecond select control signal ICMD_2 controls the access path to set theA bank 100 a as one of the second input/output port dedicated accessarea and the shared access area.

The access path to a selected memory area (e.g., the A bank 100 a) ispreferably determined by the access path control command signals Fix_1,Fix_2, and Shared. The command signal Fix_1 is for setting the A bank100 a as the first input/output port dedicated access area, the commandsignal Fix_2 is for setting the A bank 100 a as the second input/outputport dedicated access area, and the command signal Shared is for settingthe A bank 100 a as the shared access area that can be accessed at boththe first and second input/output ports. For example, an input/outputport used to access the A bank 100 a is determined by applying one ofthe access path control command signals Fix_1, Fix_2, and Shared aslogic ‘high’ and applying the remaining signals as logic ‘low’. Ofcourse, one of the access path control command signals Fix1, Fix2, andShared may be applied as logic ‘low’ and the remaining signals as logic‘high’.

The access path control command signals Fix_1, Fix_2, and Shared may beinput through the first input/output port or the second input/outputport. Further, command signals Fix_1 and Shared may be input through thefirst input/output port, and the command signal Fix_2 may be inputthrough the second input/output port.

The access path control command signals Fix_1, Fix_2, and Shared may bean MRS signal or a signal generated based on the MRS signal.Alternatively, they may be command signals generated by combiningcommand signals normally used in the semiconductor memory device or byselecting any command signal.

The data multiplexer portion 420 and 430 controls a data path betweenthe first and second input/output port control units 200 a and 300 a andthe A bank 100 a in response to the select control signals ICMD_1 andICMD_2. The first data multiplexer 420 controls a data path between thefirst port control unit 200 a and the A bank 100 a in response to thefirst select control signal ICMD_1. For example, if the first selectcontrol signal ICMD_1 is generated in response to the access pathcontrol command signals Fix_1 and Shared, the first data multiplexer 420controls to electrically connect the data line DL of the A bank 100 awith the first data sense amplifier 210 or the first data driver 220 inthe first port control unit 200 a. Accordingly, data input through thefirst input/output port may be stored in the memory cell of the A bank100 a, and data stored in the A bank 100 a may be sensed and outputthrough the first input/output port.

The second data multiplexer 430 controls a data path between the secondport control unit 300 a and the A bank 100 a in response to the secondselect control signal ICMD_2. For example, if the second select controlsignal ICMD_2 is generated in response to the access path controlcommand signals Fix_2 and Shared, the second data multiplexer 430controls to electrically connect the data line DL of the A bank 100 awith the second data sense amplifier 310 or the second data driver 320in the second port control unit 300 a. Accordingly, data input throughthe second input/output port may be stored in the memory cell of the Abank 100 a, and data stored in the A bank 100 a may be sensed and outputthrough the second input/output port.

The address multiplexer portion 440 and 450 controls the address pathbetween the first and second input/output port control units 200 a and300 a and the A bank 100 a in response to the select control signalsICMD_1 and ICMD_2. The row address multiplexer 440 controls a rowaddress path between the first port control unit 200 a and the A bank100 a in response to the first select control signal ICMD_1, andcontrols a row address path between the second port control unit 300 aand the A bank 100 a in response to the second select control signalICMD_2. For example, when the first select control signal ICMD_1 isgenerated in response to the access path control command signals Fix_1and Shared, the row address multiplexer 440 delivers a row addresssignal ADD_1 input through the first input/output port to the rowdecoder 110. When the second select control signal ICMD_2 is generatedin response to the access path control command signals Fix_2 and Shared,the row address multiplexer 440 delivers a row address signal ADD_2input through the second input/output port to the row decoder 110.Accordingly, a word line WL connected with a specific memory cell in theA bank 100 a is selected and enabled.

The column address multiplexer 450 controls a column address pathbetween the first port control unit 200 a and the A bank 100 a inresponse to the first select control signal ICMD_1, and controls acolumn address path between the second port control unit 300 a and the Abank 100 a in response to the second select control signal ICMD_2. Forexample, when the first select control signal ICMD_1 is generated inresponse to the access path control command signals Fix_1 and Shared,the column address multiplexer 450 delivers the column address signalADD_1 input through the first input/output port to the column decoder120. When the second select control signal ICMD_2 is generated inresponse to the access path control command signals Fix_2 and Shared,the column address multiplexer 450 delivers the column address signalADD_2 input through the second input/output port to the column decoder110. Accordingly, a bit line BL connected with a specific memory cell inthe A bank 100 a is selected. Here, the row address signal and thecolumn address signal are not the same but indicated by the samereference numeral since they are included in typical address signalsADD_1 and ADD_2.

FIGS. 4 to 8 illustrate examples of components of the first port controlunit 200 a and the select control unit 400 a in FIG. 3. Components ofthe second port control unit 300 a may be similarly configured as thecomponents of the first port control unit 200 a. Thus, a description ofthe components of the second port control unit 300 a is omitted.

FIG. 4 illustrates an example of the first command multiplexer 410 ofFIG. 3. The second command multiplexer 460 of FIG. 3 may be similarlyconfigured as the first command multiplexer 410.

The first command multiplexer 410 includes a logic OR circuit OR410, alogic NAND circuit NA410, and an inverter circuit IN410. The logic ORcircuit OR410 performs a logic operation on external access path controlcommand signals Fix_1 and Shared and outputs a logic signal. Forexample, the logic OR circuit OR410 outputs a logic ‘low’ signal whenthe access path command signals Fix_1 and Shared are both logic ‘low’,and outputs a logic ‘high’ signal when any one of the access pathcommand signals Fix_1 and Shared is logic ‘high’.

The logic NAND circuit NA410 performs a logic operation on the outputsignal of the logic OR circuit OR410 and an A bank select signal CMD_A1.The logic NAND circuit NA410 outputs a logic ‘low’ signal when theoutput signal of the logic OR circuit OR410 and the A bank select signalCMD_A1 received through the first input/output port are both logic‘high’, and outputs a logic ‘high’ signal, otherwise. The invertercircuit IN410 then inverts the output signal of the NAND circuit NA410and outputs the first select control signal ICMD_1.

Referring back to FIG. 3, the A bank select signal CMD_A1 contributingto generation of the first select control signal ICMD_1 and the A bankselect signal CMD_A2 contributing to generation of the second selectcontrol signal ICMD_2 are the same signal for selecting the A bank andare merely classified depending on an input/output port used to applythe signal. Accordingly, the A bank select signal CMD_A1 and the A bankselect signal CMD_A2 cannot simultaneously have a logic ‘high’ level.

FIG. 5 illustrates an example of the row address multiplexer 440 of FIG.3. The column address multiplexer 450 of FIG. 3 has a similarconfiguration as the row address multiplexer 440 except that the columnaddress multiplexer 450 receives the column address signal instead ofthe row address signal and applies an output signal to the columndecoder 120. Accordingly, a description of the column addressmultiplexer 450 is omitted.

The row address multiplexer 440 includes inverter circuits IN440, IN442,IN444, IN446, and IN448 and transfer gates TG440 and TG442. The transfergate TG440 operates when the first select control signal ICMD_1 is logic‘high’ and the second select control signal ICMD_2 is logic ‘low’.Accordingly, an address signal ADD_1 received through the firstinput/output port control unit 200 a is transferred via the transfergate TG440, latched in a latch circuit including inverters IN442 andIN446, and then sent to the row decoder 110. The other transfer gateTG442 operates when the first select control signal ICMD_1 is logic‘low’ and the second select control signal ICMD_2 is logic ‘high’.Accordingly, an address signal ADD_2 received through the secondinput/output port control unit 300 a is transferred via the transfergate TG442, latched in a latch circuit including inverters IN442 andIN446, and then sent to the row decoder 110. The transfer gates TG440and TG442 do not operate when the first select control signal ICMD_1 andthe second select control signal ICMD_2 are both logic ‘low’.Accordingly, the address signal is not applied to the row decoder 110.

The first select control signal ICMD_1 and the second select controlsignal ICMD_2 cannot simultaneously be logic ‘high’. This is because theA bank select signal CMD_A1 contributing to generation of the firstselect control signal ICMD_1 and the A bank select signal CMD_A2contributing to generation of the second select control signal ICMD_2are set not to simultaneously be logic ‘high’.

FIG. 6 illustrates an example of the first data sense amplifier 210 inthe first port control unit 200 a of FIG. 3. The second data senseamplifier 310 in the second port control unit 300 a may be similarlyconfigured as the first data sense amplifier 210.

The first data sense amplifier 210 includes PMOS transistors P210 andP212, NMOS transistors N210, N212 and N214, an inverter IN210, and aNAND circuit NA210. Unlike a conventional sense amplifier circuit, thefirst data sense amplifier 210 includes the inverter IN210 and the NANDcircuit NA210. That is, the first data sense amplifier 210 senses andamplifies data DIO_1 and DIOB_1 read from the A bank 100 a. The firstdata sense amplifier 210 sends output data FDIO_1 and FDIOB_1 to a dataoutput buffer (not shown) and/or an output driver (not shown) of thefirst port control unit 200 a.

While the conventional data sense amplifier operates in response to anapplied read command signal PREAD because the read command signal PREADis input to a gate of an NMOS transistor N214, the first data senseamplifier 210 operates in response to a combination of the read commandsignal PREAD and the first select control signal ICMD_1. For example,the first data sense amplifier 210 may operate only when both the readcommand signal PREAD and the first select control signal ICMD_1 arelogic ‘high’. This means that the first data sense amplifier 210 canoperate in response to the first select control signal ICMD_1 only whenthe A bank is either the first input/output port dedicated access areaor the shared access area. Thus, power consumption can be reduced andefficient operation can be achieved. The first data sense amplifier asdescribed above is applicable to all normally used data senseamplifiers. That is, the first data sense amplifier 210 can beimplemented by a cross-coupled data sense amplifier, a current mirrortype data sense amplifier, or the like.

FIG. 7 illustrates an example of the first data driver 220 in the firstport control unit 200 a of FIG. 3. The second data driver 320 in thesecond port control unit 300 a may be similarly configured as the firstdata driver 320.

The first data driver 220 includes PMOS transistors P220 and P222, NMOStransistors N220 and N222, a logic NAND circuit NA220, and an invertercircuit IN220. For a write operation, the first data driver 220 drivesand outputs the data Din_1 which is input through a data input buffer(not shown) in the first port control unit 200 a. Data DIO_1 output fromthe first data driver 220 is sent to the A bank 100 a via the first datamultiplexer 420.

In the conventional data driver circuit, a write command signal PWRITEor its inverted signal is input to gates of the PMOS transistor P220 andthe NMOS transistor N222. Accordingly, the data driver operates onlywhen the write command signal PWRITE (e.g., logic ‘high’) is applied.Unlike the conventional data driver circuit, the first data driver 220operates in response to a combination of the write command PWRITE andthe first select control signal ICMD_1. For example, the first datadriver 220 may operate only when the write command signal PWRITE and thefirst select control signal ICMD_1 are both logic ‘high’. This meansthat the first data driver 220 can operate in response to the firstselect control signal ICMD_1 only when the A bank is either the firstinput/output port dedicated access area or the shared access area. Thus,power consumption can be reduced and efficient operation can beachieved. The first data driver as described above is applicable to allnormally used data drivers, and other data input circuits.

FIG. 8 illustrates an example of the first data multiplexer 420 of FIG.3. The second data multiplexer 430 may be similarly configured as thefirst data multiplexer 420. The first data multiplexer 420 includes aninverter IN420 and PMOS transistors P420 and P422.

The first data multiplexer 420 controls data transmission of the A bank100 a and the first port control unit 200 a through the PMOS transistorsP420 and P422 responsive to an inverted version of the first selectcontrol signal ICMD_1. For example, data sensed from the A bank 100 acan be sent to the first port control unit 200 a only when the firstselect control signal ICMD_1 is logic ‘high’. Further, data input viathe first port control unit 200 a is sent to the A bank 100 a for thewrite operation only when the first select control signal ICMD_1 islogic ‘high’.

The circuits illustrated in FIGS. 3 to 8 are only examples provided forillustration purposes. It will be appreciated by those skilled in theart that other equivalent circuits or other variant circuits performingthe operation illustrated in FIGS. 3 to 8 are included in the scope ofthe invention.

FIGS. 9 to 15 illustrate examples of memory area allocation operationsthrough variable access path control in the semiconductor memory devicehaving the structure as described above according to an embodiment ofthe invention. These examples are provided for illustration purposes andshould not be construed to limit the scope of the invention.

The semiconductor memory device according to the invention may include aplurality of input/output ports and a memory array divided into aplurality of memory areas. For convenience of understanding, however,the semiconductor memory device is shown in FIGS. 9 to 15 as including amemory array 100 divided into four memory banks and two input/outputports.

While the embodiments have been described in connection with the A bank100 a, it will be appreciated by those skilled in the art that theconfiguration as described above can be obtained in connection withother memory banks. It is assumed that a B bank select signalcorresponding to the A bank select signal CMD_A1 applied through thefirst port control unit 200 is ‘CMD_B1’ and a B bank select signalcorresponding to the A bank select signal CMD_A2 applied through thesecond port control unit 300 is ‘CMD_B2’. In this manner, it may beassumed that a C bank select signal and a D bank select signal are‘CMD_D1’ and ‘CMD_D2’.

As previously described, the access path control command signals Fix_1,Fix_2, and Shared have the same designation but are separate andindependently applied signals for an access path to each memory bank.For example, the access path control command signals Fix_1, Fix_2, andShared as shown in FIGS. 3 to 8 are for the access path to the A bank100 a and do not affect access paths to remaining banks.

FIG. 9 illustrates an example in which the A bank 100 a and the B bank100 b are allocated as the first input/output port dedicated accessarea, and the C bank 100 c and the D bank 100 d are allocated as thesecond input/output port dedicated access area.

To allocate the A bank 100 a as the first input/output port dedicatedaccess area, an access path PA1 may be established between the A bank100 a and the first port control unit 200. That is, an A bank selectsignal CMD_A1 and the access path control command signal Fix_1 generatedonly for the A bank 100 a may be enabled. For example, as described inFIGS. 3 to 8, when the A bank select signal CMD_A1 is applied at a logic‘high’ level and when the signal Fix_1 is applied at a logic ‘high’level, the A bank 100 a is allocated as the first input/output portdedicated access area. The command signals CMD_A2, Fix_2 and Sharedremain at logic ‘low’ level.

To allocate the B bank 100 b as the first input/output port dedicatedaccess area, an access path PA2 may be established between the B bank100 b and the first port control unit 200. That is, a B bank selectsignal CMD_B1 and the access path control command signal Fix_1 generatedonly for the B bank 100 b may be enabled. For example, as in the A bank100 a, when the B bank select signal CMD_B1 is applied at a logic ‘high’level and when the signal Fix_1 is applied at a logic ‘high’ level, theB bank 100 b is allocated as the first input/output port dedicatedaccess area. The command signals CMD_B2, Fix_2 and Shared remain atlogic ‘low’ level.

To allocate the C bank 100 c as the second input/output port dedicatedaccess area, an access path PA3 may be established between the C bank100 c and the second port control unit 300. That is, a C bank selectsignal CMD_C2 and the access path control command signal Fix_2 generatedonly for the C bank 100 c may be enabled. For example, as in the A bank100 a, when the C bank select signal CMDL_C2 is applied at a logic‘high’ level and when the signal Fix_2 generated only for the C bank 100c is applied at a logic ‘high’ level, the C bank 100 c is allocated asthe second input/output port dedicated access area. The command signalsCMD_C1, Fix_1 and Shared remain at logic ‘low’ level.

To allocate the D bank 100 d as the second input/output port dedicatedaccess area, an access path PA4 may be established between the D bank100 d and the second port control unit 300. That is, when the D bankselect signal CMD_D2 is applied at a logic ‘high’ level and when thesignal Fix_2 generated only for the D bank 100 d is applied at a logic‘high’ level, the D bank 100 d is allocated as the second input/outputport dedicated access area. The command signals CMD_D1, Fix_1 and Sharedremain at logic ‘low’ level.

FIG. 10 illustrates an operation example in which the A bank 100 a isallocated as the first input/output port dedicated access area, and theB bank 100 b, the C bank 100 c, and the D bank 100 d are allocated asthe second input/output port dedicated access area.

To allocate the A bank 100 a as the first input/output port dedicatedaccess area, an access path PA1 may be established between the A bank100 a and the first port control unit 200 as previously described withreference to FIG. 9.

To allocate the B bank 100 b as the second input/output port dedicatedaccess area, an access path PA5 may be established between the B bank100 b and the second port control unit 300. That is, a B bank selectsignal CMD_B2 and the access path control command signal Fix_2 generatedonly for the B bank 100 b may be enabled. For example, when the B bankselect signal CMD_B2 is applied at a logic ‘high’ level and when thesignal Fix_2 for allocating the B bank 100 b as the second input/outputport dedicated access area is applied at a logic ‘high’ level, the Bbank 100 b is allocated as the second input/output port dedicated accessarea. The command signals CMD_B1, Fix_1 and Shared remain at logic ‘low’level.

To allocate the C bank 100 c and the D bank 100 d as the secondinput/output port dedicated access areas, access paths PA3 and PA4 maybe established as previously described with reference to FIG. 9.

FIG. 11 shows an operation example in which the A bank 100 a, the B bank100 b, the C bank 100 c, and the D bank 100 d are all allocated as thefirst input/output port dedicated access area. Thus, the multi-portsemiconductor memory device can operate as a single port semiconductormemory device.

To allocate all of the A bank 100 a, the B bank 100 b, the C bank 100 c,and the D bank 100 d as the first input/output port dedicated accessarea, access paths PA1, PA2, PA7, and PA8 may be established between therespective memory banks 100 a, 100 b, 100 c and 100 d and the first portcontrol unit 200. An allocation operation example of setting the A bank100 a and the B bank 100 b as the first input/output port dedicatedareas has been described in FIG. 9 and, thus, a description thereof isomitted.

To allocate the C bank 100 c as the first input/output port dedicatedaccess area, an access path PA7 may be established between the C bank100 c and the first port control unit 200. When the C bank select signalCMD_C1 is applied at a logic ‘high’ level and when the signal Fix_1 forallocating the C bank 100 c as the first input/output port dedicatedaccess area is applied at a logic ‘high’ level, the C bank 100 c isallocated as the first input/output port dedicated access area. Thecommand signals CMD_C2, Fix_2 and Shared remain at logic ‘low’ level.

To allocate the D bank 100 d as the first input/output port dedicatedaccess area, an access path PA8 may be established between the D bank100 d and the first port control unit 200. When the D bank select signalCMD_D1 is applied at a logic ‘high’ level and when the signal Fix_1 forallocating the D bank 100 d as the first input/output port dedicatedaccess area is applied at a logic ‘high’ level, the D bank 100 d isallocated as the first input/output port dedicated access area. Thecommand signals CMD_C2, Fix_2 and Shared remain at logic ‘low’ level.

FIG. 12 shows an operation example in which the A bank 100 a, the B bank100 b, the C bank 100 c, and the D bank 100 d are all allocated as thesecond input/output port dedicated access area. As in FIG. 11, thismulti-port semiconductor memory device can operate as a single portsemiconductor memory device. To allocate all of the A bank 100 a, the Bbank 100 b, the C bank 100 c, and the D bank 100 d as the secondinput/output port dedicated access area, access paths PA3, PA4, PA5, andPA6 may be established between the respective memory banks 100 a, 100 b,100 c and 100 d and the second port control unit 300. The allocationoperation is similar to the operation described in FIG. 11 and need notbe described in further detail.

FIG. 13 illustrates an operation example in which the A bank 100 a isallocated as the first input/output port dedicated access area, the Bbank 100 b as the shared access area, and the C bank 100 c and the Dbank 100 d as the second input/output port dedicated access area. Thiscase corresponds to a case in which there is the shared access areawhich can be accessed at both the first and second input/output ports.

An access path PA1 may be established in order to allocate the A bank100 a as the first input/output port dedicated access area. Further,access paths PA3 and PA4 may be established between the respective Cbank 100 c and the D bank 100 d and the second port control unit 300 inorder to allocate the C bank 100 c and the D bank 100 d as the secondinput/output port dedicated access area. These allocation operationshave been previously described in FIGS. 9 to 12 and need not bedescribed in further detail.

To allocate the B bank 100 b as the shared access area, the access pathPA2 with the first port control unit 200 and the access path PA5 withthe second port control unit 300 may be established. To this end, thesignal Shared for allocating the B bank 100 b as the shared access areamay first be applied at a logic ‘high’ level. In this state, an accessoperation may be performed through a desired one of the access path PA2with the first port control unit 200 and the access path PA5 with thesecond port control unit 300. For example, the B bank select signalCMD_B1 may be applied at a logic ‘high’ level through the first portcontrol unit in order to access the B bank 100 b through the firstinput/output port. The B bank select signal CMD_B2 may then be appliedat a logic ‘high’ level through the second port control unit in order toaccess the B bank 100 b through the second input/output port. Thus, theaccess path may be determined depending on an input/output port used toapply the B bank select signal CMD_B1 or CMD_B2 at a logic ‘high’ level.Even when the signal Shared for allocating the B bank 100 b as theshared access area is applied at a logic ‘high’ level, the first selectcontrol signal and the second select control signal for controlling theaccess paths PA2 and PA5 do not become a logic ‘high’ level. Thisprovides an advantage of preventing collision between the input/outputports in the shared access area. The order of applying the commandsignals Shared, CMD_B1 and CMD_B2 can be changed.

FIG. 14 illustrates an operation example in which the A bank 100 a andthe B bank 100 b are allocated as the shared access area, and the C bank100 c and the D bank 100 d as the second input/output port dedicatedaccess area. In this case, the shared access area that can be accessedat both the first and second input/output ports includes two memorybanks.

To allocate the C bank 100 c and the D bank 100 d as the secondinput/output port dedicated access area, access paths PA3 and PA4 may beestablished between the C bank 100 c and the D bank 100 d and the secondport control unit 300 as previously described in FIGS. 9 to 13. Further,an operation of allocating the B bank 100 b as the shared access areahas been described in FIG. 13 and, thus, a description thereof isomitted.

To allocate the A bank 100 a as the shared access area, the access pathPA1 with the first port control unit 200 and the access path PA6 withthe second port control unit 300 may be established. To this end, thesignal Shared for allocating the A bank 100 a as the shared access areamay first be applied at a logic ‘high’ level. In this state, an accessoperation may be performed through a desired one of the access path PA1with the first port control unit 200 and the access path PA6 with thesecond port control unit 300. For example, the A bank select signalCMD_A1 may be applied at a logic ‘high’ level through the first portcontrol unit 200 in order to access the A bank 100 a through the firstinput/output port. The A bank select signal CMD_A2 may be applied at alogic ‘high’ level through the second port control unit in order toaccess the A bank 100 a through the second input/output port. Thus, theaccess path may be determined depending on an input/output port used toapply the A bank select signal CMD_A1 or CMD_B2 at a logic ‘high’ level.This provides an advantage of preventing collision between theinput/output ports in the shared access area. The order of applying thecommand signals Shared, CMD_A1 and CMD_A2 can be changed.

FIG. 15 illustrates an operation example in which all memory banks 100a, 100 b, 100 c and 100 d are allocated as the shared access area. Asshown in FIG. 15, access paths PA1, PA2, PA5 and PA6 may be establishedto allocate the A bank 100 a and the B bank 100 b as the shared accessarea as previously described in FIGS. 13 and 14.

To allocate the C bank 100 c as the shared access area, the access pathPA7 with the first port control unit 200 and the access path PA3 withthe second port control unit 300 may be established. To this end, thesignal Shared for allocating the C bank 100 c as the shared access areamay first be applied at a logic ‘high’ level. In this state, an accessoperation may be performed through a desired one of the access path PA7with the first port control unit 200 and the access path PA3 with thesecond port control unit 300. For example, the C bank select signalCMD_C1 is applied at a logic ‘high’ level through the first port controlunit 200 in order to access the C bank 100 c through the firstinput/output port. The C bank select signal CMD_C2 is applied at a logic‘high’ level through the second port control unit in order to access theC bank 100 c through the second input/output port. In the C bank 100 c,access collision is prevented between the input/output ports. The orderof applying the command signals Shared, CMD_C1 and CMD_C2 can bechanged.

To allocate the D bank 100 d as the shared access area, the access pathPA8 with the first port control unit 200 and the access path PA4 withthe second port control unit 300 may be established. To this end, thesignal Shared for allocating the D bank 100 d as the shared access areais first applied at a logic ‘high’ level. In this state, an accessoperation may be performed through a desired one of the access path PA8with the first port control unit 200 and the access path PA4 with thesecond port control unit 300. For example, the D bank select signalCMD_D1 is applied at a logic ‘high’ level through the first port controlunit 200 in order to access the D bank 100 d through the firstinput/output port. The D bank select signal CMD_D2 is applied at a logic‘high’ level through the second port control unit in order to access theD bank 100 d through the second input/output port. In the D bank 100 d,access collision is prevented between the input/output ports, as well.The order of applying the command signals Shared, CMD_D1 and CMD_D2 canbe changed.

The semiconductor memory device as described above according to anembodiment of the invention is also useful for testing. That is, thesemiconductor memory device has an advantage when performing a testaccording to conditions by controlling the access paths in a given testenvironment.

For example, when the number of test pins of test equipment needs to bereduced, all of the memory banks 100 a, 100 b, 100 c and 100 d may beallocated as the first input/output port dedicated access area as inFIG. 11 or the second input/output port dedicated access area as in FIG.12. Then, the test may be performed through the first input/output portor the second input/output port. Accordingly, the number of the testpins can be reduced. In this case, other memory devices may be testedusing remaining test pins.

As another example, in order to reduce a test time, the memory banks 100a, 100 b, 100 c and 100 d may be divided into two groups and allocatedas the first input/output port dedicated access area and the secondinput/output port dedicated access area, as in FIG. 9. Then, testing maybe performed through the first input/output port or the secondinput/output port. Accordingly, the test time can be reduced.

In addition, efficient testing can be achieved by controlling the accesspaths according to a test environment. Control of the access paths forthe test operation may be performed through the operation as describedin FIGS. 2 to 15. In this case, however, the external command signal maybe an external command signal for test (e.g., MRS signal for test) or acombination of other input command signals.

According to the invention as described above, the access paths used toaccess the memory areas constituting the multi-port semiconductor memorydevice through the respective input/output ports may be variablycontrolled. Thus, the memory areas can be efficiently utilized by auser. In addition, the test according to a test environment is possibleand, thus, efficient testing can be performed.

Having described exemplary embodiments of the invention, it should beapparent that modifications and variations can be made by personsskilled in the art in light of the above teachings. Therefore, it is tobe understood that changes may be made to embodiments of the inventiondisclosed that are nevertheless within the scope and the spirit of theclaims.

1. A semiconductor memory device comprising: a plurality of input/outputports; a memory array divided into a plurality of memory areas; and aselect control unit to establish variable access paths between thememory areas and the input/output ports so that each memory area isaccessed through at least one of the input/output ports, wherein theselect control unit establishes the variable access paths directly inresponse to command signals external to the memory device, wherein thememory array is divided into at least four memory areas; and the selectcontrol unit is structured to establish a first data path and a firstaddress path between a first input/output port and a first of the atleast four memory areas, to establish a second data path and a secondaddress path between a second input/output port and a second of the atleast four memory areas, to establish a third data path and a thirdaddress path between the first input/output port and a third of the atleast four memory areas, and to establish a fourth data path and afourth address path between the second input/output port and a fourth ofthe at least four memory areas, in response to the command signalsexternal to the memory device, wherein when the memory device isoperating, the command signals external to the memory device aretransmitted via: at least four first signal terminals, the externalcommand signals transmitted via at least one of the first signalterminals being structured to establish a data path and an address pathbetween one of the four memory areas and the first input/output port;and at least four second signal terminals, the external command signalstransmitted via at least one of the second signal terminals beingstructured to disable a data path and an address path between one of thefour memory areas and the second input/output port.
 2. The deviceaccording to claim 1, wherein the select control unit operates in anormal operation mode in response to external command signals for anormal operation and operates in a test mode in response to externalcommand signals for a test operation.
 3. A semiconductor memory devicecomprising: first and second input/output ports; a memory array dividedinto a plurality of memory areas; and a select control unit to establishvariable access paths between the memory areas and the first and secondinput/output ports such that each memory area is variably allocated asone of a first input/output port dedicated access area, a secondinput/output port dedicated access area, and a shared access area,wherein the select control unit variably allocates the memory areasdirectly in response to command signals external to the memory device,wherein the select control unit comprises: a command multiplexer togenerate select control signals in response to the external commandsignals, wherein the select control signals allocate each memory area asone of the first input/output port dedicated access area, the secondinput/output port dedicated access area, and the shared access area; adata multiplexer to control data paths between the input/output portsand the memory areas in response to the select control signals; and anaddress multiplexer to control address paths between the input/outputports and the memory areas in response to the select control signals;wherein the select control unit variably allocates the memory areas;wherein the select control unit operates in a normal operation mode inresponse to external command signals based on an MRS code signal for anormal operation and operates in a test mode in response to externalcommand signals based on an MRS code signal for a test operation;wherein when the memory device is operating, the external commandsignals are transmitted via: at least four first signal terminals, theexternal command signals transmitted via at least one of the firstsignal terminals being structured to establish a data path and anaddress path between one of at least four memory areas and the firstinput/output port; at least four second signal terminals, the externalcommand signals transmitted via at least one of the second signalterminals being structured to disable a data path and an address pathbetween one of the four memory areas and the second input/output port;and at least four shared signal terminals, the external command signalstransmitted via at least one of the shared signal terminals beingstructured to establish a data path and an address path between one ofthe four memory areas and both the first and second input/output ports.4. In a semiconductor memory device comprising a plurality ofinput/output ports and a memory array divided into a plurality of memoryareas, a method for variably accessing the memory areas, comprising:applying external command signals to allocate the memory areas foraccess through at least one of the input/output ports; establishing dataand address paths between the memory areas and correspondinginput/output ports according to the memory area allocation; re-applyingthe external command signals to re-allocate the memory areas for accessthrough different input/output ports; and establishing new data andaddress paths between the memory areas and the corresponding differentinput/output ports according to the memory area re-allocation, whereinthe external command signals are transmitted via: at least four firstsignal terminals, the external command signals transmitted via at leastone of the first signal terminals establishing a data path and anaddress path between one of at least four memory areas and the firstinput/output port; at least four second signal terminals, the externalcommand signals transmitted via at least one of the second signalterminals disabling a data path and an address path between one of thefour memory areas and the second input/output port; and at least fourshared signal terminals, the external command signals transmitted via atleast one of the shared signals establishing a data path and an addresspath between one of the four memory areas and both the first and secondinput/output ports.
 5. The method according to claim 4, wherein when thesemiconductor memory device has first and second input/output ports,each memory area is variably allocated as one of a first input/outputport dedicated access area, a second input/output port dedicated accessarea, and a shared access area.
 6. The method according to claim 4,wherein each memory area is variably allocated based on an MRS codesignal.
 7. The method according to claim 1, wherein when the memorydevice is operating, the command signals external to the memory deviceare transmitted via at least four shared signal terminals, the externalcommand signals transmitted via at least one of the shared signalterminals being structured to establish a data path and an address pathbetween one of the four memory areas and both the first and secondinput/output ports.